Software Reliability Estimation through Reducing Cost Using Faults Tolerance Technique in Design Phase

Information Communication technologies are coming up to the decisive limits of silicon in terms of conduit width, power supply and speed. By moving towards these limits, circuits are becoming increasingly receptive to noise, which will result on intolerable rates of soft-errors. Furthermore, imperfection behavior is becoming increasingly complex resulting on increasing number of timing faults that can escape detection by fabrication testing. Thus, fault tolerant techniques will become necessary even for service applications. This work considers the implementation and improvements of a new soft error and timing error detecting technique based on time redundancy. Arithmetic circuits were used as test vehicle to validate the approach. Simulations and performance evaluations of the proposed detection technique were made using time and logic simulators. The http://www.ijccr.com VOLUME 1 ISSUE 3 MANUSCRIPT 12 NOVEMBER 2011 obtained results show that detection of such temporal faults can be achieved by means of meaningful hardware and performance cost.